IBM and the University of Texas are developing a new chip that might produce supercomputer-like performance, IBM revealed yesterday.

If development succeeds, the chip will be capable of reaching one trillion operations per second by the end of the decade, the company said.

The new TRIPS (tera-op reliable intelligently-adaptive processing system) architecture developed by the research team exploits a technique called block-oriented execution. This allows the chip to process large chunks of information in parallel, rather than waiting for a sequence of instructions to finish before taking on the next batch.

The joint project will attempt to develop a processor integrating the TRIPS architecture and up to four processor cores, IBM said. That chip is expected to contain 250 million transistors, and run at 500MHz.

Multicore designs are the future of supercomputer and server processors, IBM believes. IBM's Power4 processor (on which the G5 Power Mac is based) already incorporates a dual-core design, and Sun, Intel and HP are planning multicore processors.

The researchers hope to show that a processor with the TRIPS architecture can scale up to 10GHz, which would reach the one trillion operations per second goal. Modern supercomputers can process several trillion operations per second, but require hundreds or thousands of processors to achieve this.

Professors at the University of Texas hope to develop prototype chips by the end of 2005, and IBM Microelectronics is expected to take over volume production once the chips are ready, IBM said.