IBM's chief scientist revealed more facts about its Power5 processor at the Microprocessor Forum yesterday, MacCentral reports.
The company's Dr Balaram Sinharoy, who has been working on the design for the past several years, spoke to the industry at the event. What matters is that the G5 processor used in today's professional desktops from Apple exploits the PowerPC 970 chip, which is itself based on IBM's existing Power4 processor.
While no specific Macintosh announcements were made yesterday, Sinharoy noted the relationship, and said that such a step would be logical again as IBM engineers refine the Power5 design. The PowerPC 970 strips one processor core from the Power4 design and includes several other connection and multiprocessing sacrifices to make the chip small and affordable enough for desktops.
This means that Apple has a choice, if it maintains its relationship with IBM, that promises a positive road-map for more and improved future processor performance, which Motorola was unable to offer in its PowerPC development.
The Power5 builds on the Power4 design with enhancements made to improve performance, to allow the use of more processors in a system, and to improve power efficiency. At the same time, Sinharoy said that all code developed for the Power4 will be fully compatible with the Power5.
Like the Power4, the Power5 contains two processor cores on one chip. These cores share one 1.92MB on-die L2 cache compared with a 1.44MB L2 on-die cache on the Power4. The Power4 and Power5 both have an off-chip L3 cache, but IBM designed the L3 cache to connect directly to the L2 cache instead of between the memory controller and the processor like on the Power4. Sinharoy said that this "backdoor" cache allows the Power5 to be more scalable with multiprocessor designs. It improves performance by reducing the L3 cache latency.
The Power5 also incorporates an on-die memory controller to improve performance and reliability. Each Power5 supports up to 1,024GB of memory, compared with 512GB for each Power4. Since the memory controller is on the chip, designers need only to attach memory to the chip instead of going through a Northbridge.
The Northbridge is a component that helps the processor communicate with memory, the PCI bus, L2 cache and AGP activities. The Northbridge itself communicates with the processor using the frontside bus, which connects the CPU to main memory on the motherboard.
IBM will distribute the Power5 in a Multi-chip Module that is a 95-x-95mm block of four Power5 chips with four 36MB off-chip L3 caches. Up to 16 of these Multi-chip Modules can be implemented together for a total of 128 logical processors. The arithmetic of that is two cores per Power5 processor, four processors per module and 16 modules. Sinharoy said that all that needs to be added to a Multi-chip Module to create a system was any I/O required and memory.
The Power4 collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle. The Power5 doubles that throughput. Sinharoy said that is was not uncommon to see a "40 per cent improvement for SMT (Symmetric Multithreading) instructions," a key performance characteristic for server processors, over the Power4.
The Power5 design includes an improvement that may also be a nod at Apple. The Power5 adds a single thread performance mode that allows the processor to sacrifice some of its scalability to focus resources on completing a single thread. In layman's terms, the Power5 can ease off on some of the characteristics that allow it to easily handle many different tasks at a time to focus on one application or task. Unlike server applications, desktop applications are rarely threaded.
For now, don't expect the Power5 to be used outside of the commercial computing market. Even using a 0.13-micron copper SOI (Silicon On Insulator) manufacturing process, a single 276 million transistor Power5 chip measures 389 square millimeters – far larger than the 267 square millimeter Power4 and almost four times as large as a PowerPC 970.
IBM also added a power management scheme to the Power5 that Sinharoy claims will drastically reduce power consumption and heat generation. His presentation contained no information on the power needs or heat dissipation characteristics of the Power5.
Sinharoy said that the Power5 is working in IBM's labs now and is on schedule to ship next year; however, he made no mention of benchmark performance or clock speed of the new processor. Sinharoy said that a Power5+, which will be similar to the Power5 but manufactured using a 90-nanometer process, is tentatively scheduled for 2005. Finally, Sinharoy said that a Power6 is "well underway" and scheduled for introduction in 2006.