IBM will provide news and update analysts about its business strategy for its Power line of microprocessors at a press event in New York on Wednesday.
The company is also expected to provide details on the Power5 microprocessor that will form the basis of its next line of eServer pSeries Unix systems, code-named Squadron. Apple's current G5 processor is based on IBM's Power4 architecture, which precedes the Power5.
IBM is billing the event as one that will have: "Widespread implications for the gaming, communications and computing industry," and is promising "significant announcements and important new business strategies," according to an invitation to the event, which is being held at New York's W Hotel.
IBM will be looking to position Power5 as more than simply a "big, monolithic enterprise processor," said Gordon Haff, an analyst with research company Illuminata.
"IBM has had a lot of success with Power outside of the data centre, which is perhaps not as widely recognized as IBM would like it to be," he said. "They're looking to build on that success."
One item that could be on the agenda Wednesday is a next-generation microprocessor for broadband devices, code-named "Cell." In 2001, IBM, Sony and Toshiba launched a five-year, $400 million effort to design a new processor for networked consumer devices.
Nearly 300 chip designers and computer architects from the three companies have been working on Cell at an IBM research facility in Austin, Texas, and the project is expected to begin delivering products by 2005.
Though it remains unclear whether Wednesday's event will serve as the formal launch of the Power5 processor, analysts are expecting to hear some new details on the chip.
IBM previously has stated that Power5 will be a dual-core processor that will use multithreading technology to support as many as two "virtual processors" per core, which means that as far as the operating system is concerned, it will appear to contain four processors.
At 389 square millimeters in surface area, the 276 million-transistor Power5 will be much larger than the 267 square millimeter Power4. It will also support as much as 1,024GB of system memory – twice as much as the Power4 – and is expected to be used in much larger SMP (symmetric multiprocessing) systems than are currently supported by the Power4. IBM's largest pSeries server, the p690, currently scales to as many as 32 processors. That limit is expected to double to 64 processors when the Power5 systems begin shipping.