Intel will announce plans to build chips for handhelds and mobile phones on a separate version of its future manufacturing technology that greatly minimizes transistor current leakage, according to the company's manufacturing chief.
The company is getting ready to introduce its first chips built on its 65 nanometre process technology, which is a generational advance over the company's current chip-making blueprint. While Intel has made strides in reducing the problem of power leakage with its upcoming generation of PC and server processors, a more aggressive approach is needed to produce future chips for battery-operated devices, said Mark Bohr, a senior fellow and director of Intel's process architecture and implementation.
Power in tiny parcels
Power consumption, and the related problem of dissipation, were central to Intel's development of its 65nm manufacturing technology. A nanometre is one billionth of a metre, and the specific number attached to a generation refers to the average size of features on the chip.
Transistors have now grown so small at the 90nm generation - currently used to build Intel's most advanced chips - that the electrical power used to run the transistors can leak out of the chip as heat. In some cases, power can even leak out of a transistor that isn't running.
This problem was exacerbated by Intel's marketing and design strategy in previous years, which called for chips with faster and faster clock speeds. More power is required to raise a chip's clock speed, or the number of instructions it completes in a second.
Late awakening for market leader
Intel has belatedly realized it needs to get power consumption and leakage under control through both design and manufacturing strategies. It has announced plans to redesign future chips around low-power concepts and has made advances in manufacturing technology that reduce the power consumption problem in transistors for PC and server processors.
But for some chips, such as the ones that power mobile phones, an even more aggressive power management strategy is required, Bohr said. This led to the development of a second 65nm manufacturing process that significantly reduces power leakage in chips designed for devices that do not require as much performance as PCs or servers, he said.
The second process is basically the same as the main 65nm process used to build upcoming chips such as Yonah, a dual-core version of the Pentium M notebook processor that is expected to arrive early next year, Bohr said. However, it uses a few different manufacturing techniques designed to contain leakage at the expense of transistor switching speeds, he said.
For example, Intel raised the threshold voltage of transistors made with the low-power process technology. A transistor's threshold voltage is the amount of power needed to change the state of that transistor. In some cases, 90nm transistors could be inadvertently activated by small amounts of power leaking from one side of the transistor (the source) to the other side (the gate), and raising the threshold voltage reduces the likelihood of that problem, Bohr said.
SOI ‘so-so’, Intel claims
Former Intel competitor Transmeta has reorganized its business around licensing a technology that actively raises and lowers the threshold voltage of a transistor depending on performance requirements. Intel's approach is static, in that the threshold voltage has been raised for all transistors made using the low-power process, an Intel spokesman said.
Intel has also reduced the amount of current that leaks from the junction between a transistor and its silicon base. IBM and Advanced Micro Devices use a technology known as SOI (silicon on insulator) to reduce leakage from the transistor into the substrate of the chip.
Intel has shown little interest in SOI, which has been credited with reducing current leakage on AMD's newest chips. Intel considers it too costly to implement, Bohr said.
SOI controls leakage across the entire transistor, while Intel has focused on controlling junction leakage around the edge of a transistor, where 90 per cent of junction leakage takes place, Bohr said. The company declined to specify exactly how it is controlling junction leakage.
The gates on transistors built with the low power process will be thicker than their counterparts on transistors for PC and server processors, Bohr said. This reduces the speed at which the transistor switches from an "on" state to an "off" state, affecting performance but reducing a significant source of leakage, he said.
In fact, all these techniques reduce the performance of transistors. But not every chip requires the same amount of performance as a PC processor, Bohr said. The new process will provide Intel's chip designers with the means to create low-power chips for phones, handhelds, or devices that haven't even reached the drawing board, he said.
Intel plans to have the low-power manufacturing process up and running in about a year's time, Bohr said. It is currently being developed in Fab D1D, the company's manufacturing research and development facility in Hillsboro, Oregon.
Texas Instruments, the leader in chips for mobile phones, announced its own set of power management technologies for the 65nm generation of its manufacturing processes on Monday. Its SmartReflex technology is a combination of hardware and software that minimizes the amount of power needed to perform certain functions on mobile phone chips, the company said in a release.